memory
RSS memoryHigh-Bandwidth Address Generation Unit
White Paper This paper describes an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed Address GENeration (AGEN) unit operates with a modified version of the low-order... [11 Jul 2008]
Scalable VPN Routing Via Relaying
White Paper As a result, router memory in the provider's network has become a key bottleneck in provisioning new customers. Enterprise customers are increasingly adopting MPLS (Multiprotocol Label Switching) VPN (Virtual Private Network) service that offers... [11 Jul 2008]
High-Bandwidth Address Translation for Multiple-Issue Processors
White Paper As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency. In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level... [11 Jul 2008]
Scalability, Fidelity, and Containment in the Potemkin Virtual Honeyfarm
White Paper A prototype honeyfarm system has built, called Potemkin that exploits virtual machines, aggressive memory sharing, and late binding of resources to achieve this goal. The rapid evolution of large-scale worms, viruses and bot-nets have made Internet... [11 Jul 2008]
The Effect of Contention on the Scalability of Page-Based Software Shared Memory Systems
White Paper This paper demonstrates the profound effects of contention on the performance of page-based software distributed shared memory systems; as such systems are scaled to a larger number of nodes. It argue that applications that suffer from increases in... [11 Jul 2008]
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors
White Paper Destination-set prediction can improve the latency/bandwidth tradeoff in shared-memory multiprocessors. The destination set is the collection of processors that receive a particular coherence request. [11 Jul 2008]
An Implementation Framework for Trajectory-Based Routing in Ad Hoc Networks
White Paper The nodes are low-memory, low-powered, and they cannot maintain routing tables large enough for well-known routing protocols. Routing in ad hoc networks is a complicated task because of many reasons. Because of that, greedy forwarding at... [11 Jul 2008]
PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects
White Paper With processor and memory technologies pushing the performance limit, the bottleneck is clearly shifting towards the system interconnect. Any solution that addresses PCI's bus-based interconnect, which has serious scalability problems, must also... [11 Jul 2008]
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
White Paper A mini-graph is a dataflow graph that has an arbitrary internal size and shape but the interface of a singleton instruction: two register inputs, one register output, a maximum of one memory operation, and a maximum of one (terminal) control... [11 Jul 2008]
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
White Paper The solutions that proposed in this are: low-complexity commit in constant time to eliminate the task commit bottleneck, a memory-based overflow area to eliminate stall due to speculative buffer overflow, and exploiting high-level access patterns... [11 Jul 2008]
Enterprise-Quality Security Devices for the End User
White Paper Both Innominate products use the Intel IXP425 network processor, the Intel 28F128J3 Strata Flash memory, and the Intel LXT973 10/100Mbps Ethernet PHY transceiver. With everything and everyone connected to the Internet - virtually anywhere at... [11 Jul 2008]
Operating System Multilevel Load Balancing
White Paper Thus, for NUMA systems with three or more memory access levels, the constructed hierarchy does not represent correctly the machine's topology. This paper describes an algorithm that allows Linux to per-form multilevel load balancing in NUMA computers. [10 Jul 2008]
New Challenges in Dynamic Load Balancing
White Paper Increased use of heterogeneous computing architectures requires partitioners that account for non-uniform computing, network, and memory resources. Data partitioning and load balancing are important components of parallel computations. [10 Jul 2008]
Optimizing Pattern Matching for Intrusion Detection
White Paper A memory efficient variant uses sparse matrix storage to reduce memory requirements and further improve performance on large pattern groups. This paper presents an optimized version of the Aho-Corasick algorithm. [10 Jul 2008]
Load Balancing With Memory
White Paper This paper show that similar performance gains occur by introducing memory. A standard load balancing model considers placing n balls into n bins by choosing d possible locations for each ball independently and uniformly at random and sequentially... [10 Jul 2008]
