circuits bit-error rate
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Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits
White Paper Typically, a maximum Bit-Error Rate (BER) of 10 - 12-10 - 15 is required. High speed serial data links are expected to transmit data at very high rates with very high fidelity. Today... [29 Aug 2009]
Jitter Tolerance Analysis of Clock and Data Recovery Circuits Using Matlab and VHDL-AMS
White Paper In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, the paper presents two methods to analyze the jitter tolerance of such links, based... [22 Oct 2008]
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
White Paper Clock and Data Recovery (CDR) circuits incorporating bang-bang (binary) Phase Detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required... [22 Oct 2008]
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