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HP StorageWorks XP Disk Array and Mainframe White Paper: Direct Attached Vs. Switched Vs. Cascaded FICON
White Paper Further, Cascaded FICON allows one connect data centers together over fewer fibers or circuits, enabling a more cost effective disaster recovery or business continuity solution. With the speed of FICON... [01 Sep 2009]
Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits
White Paper High speed serial data links are expected to transmit data at very high rates with very high fidelity. Today speeds approaching 10 Gb/s are becoming common with 40 Gb/s on the horizon. Typically, a maximum Bit-Error Rate (BER) of 10 -... [29 Aug 2009]
A 200-Mbps 2-Gbps Continuous-Rate Clock-and-Data-Recovery Circuit
White Paper To receive the data with different bit rates over a wide range without the harmonic-locking issue, two kinds of Clock-and-Data-Recovery (CDR) circuits existed in literature. The retiming... [29 Aug 2009]
A Wide-Tracking Range Clock and Data Recovery Circuit
White Paper SCALING of CMOS technology has progressed relentlessly for the past several decades and brought unprecedented benefits to digital Integrated Circuits (ICs). In order for the improvements of individual ICs to benefit the... [29 Aug 2009]
Jitter Tolerance Analysis of Clock and Data Recovery Circuits Using Matlab and VHDL-AMS
White Paper In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, the paper presents two methods to analyze the jitter tolerance of... [22 Oct 2008]
Simulation Model of Digital Clock and Data Recovery for Strongly Disturbed Signals
White Paper All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The paper describes VHDL-AMS simulation model... [22 Oct 2008]
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
White Paper Clock and Data Recovery (CDR) circuits incorporating bang-bang (binary) Phase Detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and... [22 Oct 2008]
A Multiple-Rotating-Clock-Phase Architecture for Digital Data Recovery Circuits Using Verilog-A
White Paper This paper presents an oversampling Data Recovery (DR) architecture using Verilog-A that employs a novel Multiple-Rotating-Clock-Phase (MRCP) concept for its operation. The MRCP-DR architecture is a variant of the... [22 Oct 2008]
A 1O-Gb/s CMOS Clock and Data Recovery Circuit
White Paper Clock and Data Recovery (CDR) circuits operating in the 1O-Gb/s range have become attractive for the optical fiber backbone of the Internet. While CDR circuits operating at 10-Gbls and... [22 Oct 2008]
Open-Loop Clock and Data Recovery Systems
White Paper CDR circuits typically use PLLs, but their complexity presents several design challenges : the input data stream is random and is usually in Non-Return-to-Zero (NRZ) data format, and little energy exists at the clock... [22 Oct 2008]
Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems
White Paper Clock recovery using Phase-Locked Loops (PLL) with binary (bang-bang) or ternary-quantized phase detectors has become increasingly common starting with the advent of fully monolithic Clock and Data... [07 Oct 2008]
Ten things not to do with your data
News The circuits were ruined and the drive failed to work. Deaths at the hands of bananas, smelly socks and WD-40 are some of the unusual fates to have befallen innocent hard drives, according to a data... [16 Nov 2006]
How CIOs mitigate VoIP's risks
Comment Most voice networks in organisations are under-utilised, under-supported and have very little resilience compared with the backup links and redundancy built into most data networks, even if its ISDN backups to leased... [09 Sep 2004]
