memory bus
RSS memory busStudy of Network on Chip Resources Allocation for QoS Management
White Paper The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. Predictability for computation, memory and communication components are needed to build up real-time SoC. [18 Jul 2008]
Memory and Network Bandwidth Aware Scheduling of Multiprogrammed Workloads on Clusters of SMPs
White Paper However, contention among processors for access to shared resources, as is the main memory bus and the NIC can limit their efficiency significantly. The algorithm selects the processes to be coscheduled so as not to saturate nor underutilize the... [11 Jul 2008]
PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects
White Paper Any solution that addresses PCI's bus-based interconnect, which has serious scalability problems, must also protect the huge legacy infrastructure. With processor and memory technologies pushing the performance limit, the bottleneck is clearly... [11 Jul 2008]
ZBT SRAM Controller Reference Design for APEX II Devices
White Paper As communication systems require more low-latency, high-bandwidth interfaces for peripheral components, designs need high-throughput memory with efficient bus utilization. IDT, Micron, and Motorola developed the new zero-bus turnaround (ZBT) SRAM... [03 Jul 2008]
HP F8 Architecture
White Paper HP designed the F8 architecture with increased memory bandwidth, a non-blocking crossbar switch that improves bus efficiency, and PCI Hot-Plug and PCI-X capabilities in the I/O subsystem. The F8 architecture includes HP Hot-Plug RAID Memory - a new... [03 Jul 2008]
Intel 925X Express Chipset Memory Configuration Guide
White Paper Intel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with DDR2-533 and an Intel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 800... [03 Jul 2008]
Intel 915G Express Chipset Memory Configuration Guide
White Paper Intel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with DDR2-533 and an Intel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 800... [03 Jul 2008]
APEX PCI Development Kit Flash Memory Controller White Paper
White Paper Data written into the flash memory device is transferred across the 32- or 64-bit PCI bus. This white paper describes the flash memory controller, which works together with APEX PCI Development Kit If you want to integrate the flash memory... [03 Jul 2008]
DDR Memory Technology
White Paper Rapid growth in both CPU and motherboard bus speeds, however, spurred development of improved DRAM methods to provide performance equal to faster and faster system capabilities. Where originally, nearly all PC system memory was confined to FPM... [03 Jul 2008]
InfiniBand Technology for Embedded Systems
White Paper InfiniBand Technology is switched fabric architecture that replaces the parallel I/O bus in a server with a System Area Network. A Computing End Node uses a HCA (Host Channel Adapter) to connect the processor's memory controller to the InfiniBand... [03 Jul 2008]
Intel 915G/915GV Express Chipset Memory Configuration Guide
White Paper Intel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with DDR2-533 and an Intel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 800... [03 Jul 2008]
Embedded DRAM Technologies: Comparisons and Design Tradeoffs
White Paper Even more importantly, embedding DRAM enables higher bandwidth by allowing a wider on-chip bus, and saves power by eliminating DRAM I/O. The use of embedded DRAM technology has become widespread, especially in higher-end system designs, because of... [03 Jul 2008]
IBM eServer pSeries 690 Configuring for Performance
White Paper IBM eServer pSeries 690 server takes advantage of the significantly faster POWER4+ processor, upgraded system architecture and a faster system bus, memory subsystem and input/output (I/O) subsystem. Appropriately configuring the pSeries 690 server... [03 Jul 2008]
IBM eServer pSeries 655 Ultra Dense Cluster Block for High Performance Computing
White Paper The IBM eServer pSeries 655 is a 4- or 8-symmetric multiprocessing (SMP) server delivering speed advantages—thanks to the powerful POWER4+ processor and its associated system architecture-and fast system bus, memory and input/output (I/O) subsystems. [03 Jul 2008]
USB and KVM Switches: The Rise of USB in the Data Center
White Paper The past decade or so have seen the Universal Serial Bus (USB) grow from pipe dream into the de facto standard to power devices such as peripherals, portable memory devices, video game consoles, PDAs, and portable media players. [27 Mar 2008]
