memory buses
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Inbox: Antique computing, Segway protest and ID cards
Comment Think about the number of school buses used to transport children from villages to ever consolidating schools. We certainly learned to be efficient with memory space. A story concerning fibre broadband... [11 Sep 2008]
Careless commuters put corporate data at risk
News Transport for London, which covers London Underground and London buses, said it handled 10,614 lost mobile phones and 5,718 electronic items including cameras and laptops in the last year. On a more serious note,... [24 Jan 2005]
Configurable Memory Organisation for Communication Applications
White Paper The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. A configurable memory... [04 Oct 2004]
High-Speed Link Loop Architecture for the IBM eServer iSeries Server
White Paper High-speed link (HSL) is the name of the system internal bus technology of the latest iSeries servers that connects system processors to industry-standard PCI buses. As faster processors, larger cache, faster... [24 Sep 2004]
Jobs hails 'uber Mac': 'Better than any Windows PC'
News Aside from the new chip, the new Power Macs will feature other architectural changes, including the addition of 1GHz front-side buses, USB 2.0 ports and serial ATA drives. The entry-level model comes with a 1.6GHz... [24 Jun 2003]
Intel and Via kiss and make up
News The buses and pin structures can't be compatible with Intel products. For the first three years, Intel has agreed not to sue Via for making processors that come with buses and pin structures that are... [08 Apr 2003]
Smartcard ticketing going Underground
News TranSys, a consortium of companies led by Electronic Data Systems (EDS) and Cubic Transportation Systems (CTS), designed the system and has so far outfitted 6,000 buses and 255 Tube stations to use the cards. [20 Nov 2002]
Intel developing chip with two brains
Comment The approach saves on computing real estate and can increase efficiency because the chip cores can share cache memory or buses. Meanwhile, vacant space on the memory controller inside... [21 Aug 2002]
