memory instruction
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Inbox: Antique computing, Segway protest and ID cards
Comment I can recall "playing" with an old 803 in my formative IT years as an operator working at Keele Uni - messing about with the instruction set and the mag film to program tunes on the console speaker etc. [11 Sep 2008]
Photos: Britain's first business computer
Photo The user would manually set up an address in memory, the instruction would be programmed into that memory and then stored there. The process was repeated step-by-step, loading... [05 Sep 2008]
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
White Paper Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniprocessor system. Even if non-determinism is... [04 Aug 2008]
High-Bandwidth Address Translation for Multiple-Issue Processors
White Paper In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth demands on the address... [11 Jul 2008]
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
White Paper A mini-graph is a dataflow graph that has an arbitrary internal size and shape but the interface of a singleton instruction: two register inputs, one register output, a maximum of one memory operation,... [11 Jul 2008]
Celebrating 60 years of computing
News According to university press officer Alex Waddington, the computing speed was 1.2 milliseconds per instruction, equivalent to a clock speed of slightly under 1kHz - more than two million times slower than a typical... [20 Jun 2008]
White Paper: Removable Storage Media Add Flexibility to Modern Day PLC's
White Paper Instruction sets in today's IEC-61131 programming development systems support data formatting, read and write file operations, and other data organization tools for conveniently sharing data with analysis tools such as... [23 Aug 2007]
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
White Paper This paper proposes Microarchitecture-Based Introspection (MBI), a transient-fault detection technique, which utilizes the wasted processing bandwidth during long-latency cache misses for redundant execution of the... [08 May 2007]
Buffering Database Operations for Enhanced Instruction Cache Performance
White Paper This paper proposes techniques to buffer database operations during query execution to avoid instruction cache thrashing. The benefit is mainly from better instruction locality and better hardware branch... [08 May 2007]
Architectural Support for Software-Based Protection
White Paper The first part of this paper shows how modest Instruction Set Architecture (ISA) support can replace such guard code with single instructions. Control-Flow Integrity (CFI) is a property that guarantees program control... [08 May 2007]
Improving Database Performance on Simultaneous Multithreading Processors
White Paper Simultaneous MultiThreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. This paper investigates three thread-based techniques to exploit SMT architectures... [08 May 2007]
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
White Paper If such a load instruction incurs a long-latency cache miss during runahead execution, its data value is predicted by subtracting the stable delta from its effective address. While runahead execution is effective at... [08 May 2007]
Low-Power Implementation of an OFDM Based Channel Receiver in Real-Time Using a Low-End Media Processor
White Paper The implementation of advanced channel receivers using low-end multimedia instruction set processors is a productive, flexible and cost effective alternative to custom hardware. This paper focuses on the exploration of... [18 Apr 2007]
Developing and Tuning Applications on UltraSPARC T1 Chip Multithreading Systems
White Paper This new processor design provides multiple physical-instruction execution pipelines and several active thread contexts per pipeline. CMT technology, like that available in the UltraSPARC T1 processor, provides a new... [07 Jun 2006]
FR-V Single-Chip Multicore Processor: FR1000
White Paper To realize the low power consumption and low-cost equipment needed to decode high definition broadcasts, Fujitsu has developed a single-chip multicore processor FR1000 that integrates four 8-way, Very Long Instruction... [02 Jun 2006]
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