memory system performance
Power-Aware Code Scheduling for Clusters of Active Disks
White Paper Each individual active disk (which includes an embedded processor, disk(s), caches, memory, and interconnect) can perform some application level processing; but, more importantly, the active disks can collectively perform parallel Input/Output (I... [11 Aug 2008]
Analyzing the Scalability of Graph Algorithms on Eldorado
White Paper Unlike the MTA-2, this platform will have a more constrained network bisection bandwidth and will pay a high penalty for random memory accesses. The Cray MTA-2 system provides exceptional performance on a variety of sparse graph algorithms. [04 Aug 2008]
Scalability and Performance of HP ProLiant BL45p Server Blade With Citrix Presentation Server x64
White Paper These constraints are the result of restrictions imposed by the operating system in the area of kernel memory, limiting the ability to take full advantage of server capacity. This white paper gives IT professionals information on the performance... [04 Aug 2008]
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
White Paper Even if non-determinism is tightly controlled by adding conventional QoS support, it is generally difficult to find the minimal hardware resource request settings (e.g.memory bandwidth) for a given user-level performance goal (e.g.transactions per... [04 Aug 2008]
High-Bandwidth Address Translation for Multiple-Issue Processors
White Paper As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency. In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level... [11 Jul 2008]
PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects
White Paper With processor and memory technologies pushing the performance limit, the bottleneck is clearly shifting towards the system interconnect. Any solution that addresses PCI's bus-based interconnect, which has serious scalability problems, must also... [11 Jul 2008]
Optimizing Pattern Matching for Intrusion Detection
White Paper A memory efficient variant uses sparse matrix storage to reduce memory requirements and further improve performance on large pattern groups. This design represents a significant enhancement to the author's original implementation released in 2002... [10 Jul 2008]
Bandwidth Reduction for Video Processing in Consumer Systems
White Paper Due to the fast increase of required computational power of consumer systems, the data communication to and from the o -chip memory has become the bottleneck in the overall system performance (memory wall problem). [10 Jul 2008]
Comparative Performance Analysis of RDMA-Enhanced Ethernet
White Paper New technologies are emerging to bridge the performance gap (e.g.latency) between these classes of high-performance interconnects by adapting advanced communication methods such as Remote Direct-Memory Access (RDMA) to the Ethernet and IP... [10 Jul 2008]
Towards Dynamic Load Balancing Using Page Migration and Loop Re-Partitioning on Omni/SCASH
White Paper This paper reports the ongoing work on dynamic load balancing extension to Omni/SCASH which is an implementation of OpenMP on Software Distributed Shared Memory, SCASH. Using this dynamic load balancing mechanisms, it is expected that programmers... [10 Jul 2008]
NIC-Based Intrusion Detection: A Feasibility Study
White Paper Functions such as signature-based and anomaly-based packet classification are performed on the NIC, which has its own processor and memory. This paper presents and evaluates a NIC-based network intrusion detection system. [09 Jul 2008]
Ethernet Network Traffic Accelerators
White Paper The Ethernet migration to 10 Gbps has exceeded microprocessor performance and memory bandwidth. With systems unable to cope with the bandwidth demands, systems are relying on the traditional approach of the operating system throttling back the data... [08 Jul 2008]
Testing .NET Applications
White Paper Learn which tools can be employed by developers early in the development life-cycle to find memory errors, performance bottlenecks and ensure complete code coverage. QA/Testing professionals will also learn about software quality tools used to... [03 Jul 2008]
Managed Runtime Technologies - Enterprise Java Performance: Best Practices
White Paper It examines the performance of the software/hardware stack, first from the system-level perspective (topology, I/O, network), then from the top software layer (application level), through the middle layer (Java Virtual Machine), and down to the... [03 Jul 2008]
Upgrading a Customer Database System: Itanium-Based Platform Boosts System Performance and Stability
White Paper Because the Itanium-based platform has a faster processing speed and a much larger memory cache, one found that one was able to improve overall performance, even with the database-intensive applications. [03 Jul 2008]
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