processing the physical hiperdispatch
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Introduction to HiperDispatch Management Mode with z10
White Paper HiperDispatch was designed to (1) minimize the z10 hardware performance degradation caused by processor cache misses, and (2) maximize the amount of CPU processing power associated with any single logical processor. [17 Jul 2008]
Planning Considerations for HiperDispatch Mode
White Paper The logical processors for one LPAR image receive an equal share for equal access to the physical processors under PR/SM LPAR control. For example, if the weight of a logical partition with four logical processors results in a share of two physical... [30 Apr 2008]
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