processor cache
RSS processor cacheIntroduction to HiperDispatch Management Mode with z10
White Paper HiperDispatch was designed to (1) minimize the z10 hardware performance degradation caused by processor cache misses, and (2) maximize the amount of CPU processing power associated with any single logical processor. [17 Jul 2008]
MCA Error Recovery: HP-UX Feature for Recovering From Machine Check Aborts
White Paper Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure. HP Integrity servers provide superior reliability and availability. [05 Jun 2008]
IntelŪ ItaniumŪ 2 Processor Quick Reference Guide
White Paper The new IntelŪ ItaniumŪ 2 processor with 6M L3 cache accelerates the momentum of the Intel Itanium 2 processor family. Find out why this system would be beneficial to your organization. [10 Apr 2008]
Near Fine Grain Parallel Processing Using a Multiprocessor With MAPLE
White Paper The DTC realize a software controlled cache by instructions which are generated by the compiler. The MAPLE core is a simple RISC processor which executes every operation in a fixed time and realizes direct register to register transfer. [04 Mar 2008]
Cache Optimization for Coarse Grain Task Parallel Processing Using Inter-Array Padding
White Paper This paper describes inter-array padding to minimize cache conflict misses among macro-tasks with data localization scheme which decomposes loops sharing the same arrays to fit cache size and executes the decomposed loops consecutively on the same... [03 Mar 2008]
Itanium revisited - one year on
Comment But the new Itanium chip has two processor cores like Montecito and the same amount of cache. Hardly mentioned at the Intel Developers Forum this September, the next-generation Itanium 9100 processor line, codenamed Montvale, was released in a... [13 Dec 2007]
Dynamic Adaptive File Management in a Local Area Network
White Paper Furthermore, data is transferred directly to the client's cache from network-attached disks, thus avoiding copies from a disk to the server buffer and then over the network to the client. Dynamo uses a cooperative cache management which employs a... [05 Dec 2007]
The Intel Itanium 2 Processor With 6M L3 Cache: Architected for Demanding Enterprise and Technical Applications
White Paper The new Intel Itanium 2 processor with 6M L3 cache accelerates the momentum of the Intel Itanium 2 processor family. The Itanium 2 processor with 6M L3 cache delivers new levels of compute-parallelism, scalability and reliability for Databases... [14 Nov 2007]
Building Cutting-Edge Server Applications: Intel Xeon Processor Family Features the Intel NetBurst Microarchitecture With Hyper-Threading Technology
White Paper The Intel NetBurst microarchitecture significantly enhances P6 microarchitecture as well as introduces new innovative performance related features, such as Execution Trace Cache, Rapid Execution Engine, Hyper-Pipelined technology, and Streaming... [15 Sep 2007]
Speculative Precomputation: Long-Range Prefetching of Delinquent Loads
White Paper It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the... [15 Sep 2007]
Performance Analysis of IOP Processor (XScale) for SAN/NAS Application
White Paper In NAS and SAN environment, data is transferred from a server to the storage subsystem, and IOP subsystem memory is used as cache to store data temporarily before writing to the storage devices. Over the past several years, applications such as... [23 Aug 2007]
Intel Xeon Processor MP
White Paper The Intel Xeon processor MP, now available up to 3 GHz and 4 MB iL3 cache, provides a seamless upgrade path for higher performance. This paper describes the Intel Xeon processor MP, designed specifically for 4-way, (and above), multi-processor (MP... [03 Aug 2007]
Cornell Theory Center: Demonstrating the Value of Intel Itanium Architecture in High Performance Computing
White Paper The Intel Itanium architecture is an outstanding choice for HPC solutions, offering a 64-bit address space, outstanding floating-point performance and memory bandwidth, and large cache memories. Equally important, the Itanium processor family... [30 Jul 2007]
Cache in on the Enterprise Library Caching Block for .NET 2.0
White Paper After storing such items in the local cache, one can improve application throughput by returning the cached output in response to subsequent requests rather than recreating them from scratch every time. [02 Jul 2007]
An Enterprise Database Performance Comparison of the Dell PowerEdge 6850 and the Sun Fire V490 UltraSPARC Server
White Paper The latest generation from vendors such as Intel and Sun feature two processor cores and a large L3 cache on the processor module. Computer processor vendors continue to bring out higher performing processors. [05 Jun 2007]
