processors high performance
Characterizing Secure Dynamic Web Applications Scalability
White Paper The vertical scalability of the server is measured if running with different number of processors, determining the impact of adding more processors on server saturation. To obtain scalable application servers, a complete analysis to determine the... [18 Jul 2008]
High-Bandwidth Address Translation for Multiple-Issue Processors
White Paper In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth demands on the address translation mechanism. [11 Jul 2008]
Exploring the VLSI Scalability of Stream Processors
White Paper Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area- and energy-efficient than conventional programmable architectures. [11 Jul 2008]
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
White Paper This paper considers the efficiency of packet buffers used in packet switches built using Network Processors (NPs). Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch, inefficient... [11 Jul 2008]
Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth
White Paper Fingerprinting summarizes a processor's execution history in a hash-based signature; differences between two mirrored processors are exposed by comparing their fingerprints. The result of this study shows that fingerprinting is the only error... [11 Jul 2008]
Programmable Gigabit Ethernet Packet Processor Design Methodology
White Paper The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many applications. Indeed, this forwarding engine requires a high degree of flexibility to support a large... [10 Jul 2008]
An FPGA-Based Dynamic Load-Balancing Processor Architecture for Solving N-Body Problems
White Paper This research focuses on the use of reconfigurable processors for solving computationally intensive scientific applications, with an added twist. Reconfigurable computing has emerged as a key technology in the field of high performance and embedded... [10 Jul 2008]
Distributed Utilization Control for Real-Time Clusters With Load Balancing
White Paper Such clusters must adaptively control the CPU utilizations of many processors in order to maintain desired soft real-time performance and prevent system overload in face of unpredictable workloads. Recent years have seen rapid growth of online... [10 Jul 2008]
Network Processor Load Balancing for High-Speed Links
White Paper While transmission rates already achieve speeds beyond 40 Gb/s, today's network processors are only slowly approaching 10 Gb/s. This paper presents a load-balancing scheme that enables system designers to bridge the performance gap using multiple... [10 Jul 2008]
Removing Cell Demultiplexing Performance Bottleneck in ATM Pseudo Wire Emulation Over MPLS Networks
White Paper Supporting cell multiplexing, however, can create performance bottleneck at the egress Provider Edge (PE) where fully programmable network processors are used to do the cell demultiplexing. Performance analysis shows that the use of just two... [10 Jul 2008]
BEA and HP Create Stable, High Performance Customer Self Service Portal for Swiss Life in Belgium
White Paper Swiss Life is using an HP-UX environment across three HP RP8400 UX servers, each with 10 processors.ensures BEA WebLogic Server 8.1 also offers clients a secure ePortal environment. The challenge was to increase application performance and enable... [10 Jul 2008]
Aerospace Firm Attracts Customers With High-Performance Computing
White Paper After researching processors and interconnect technology, Andrews Space elected to create its new parallel-processing computing cluster by linking Dell servers through a Cisco SFS 7000P InfiniBand Server Switch. [08 Jul 2008]
Ethernet Network Traffic Accelerators
White Paper Even the highest performance processors (CPUs) are unable to keep pace with the demands of the network. The Ethernet migration to 10 Gbps has exceeded microprocessor performance and memory bandwidth. This approach does not address the problem and... [08 Jul 2008]
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
White Paper This system, called LineSnort, parallelizes Snort using concurrency across TCP sessions and executes those parallel tasks on multiple low-frequency pipelined RISC processors embedded in the NIC. This paper presents and evaluates a strategy for... [07 Jul 2008]
HP Integrity gets Parallel virtualisation
News HP's Integrity range of systems runs on the Intel Itanium line of processors. Parallels Virtuozzo Containers on the HP Integrity server is available now for $4,500 to utilise two processors. Serguei Beloussov, chief executive of Parallels, said... [03 Jul 2008]
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