cmos
RSS cmosCMOS Optical Receiver Chipset for Gigabit Ethernet Applications
White Paper This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a TransImpedance Amplifier (TIA) and a Clock and Data Recovery (CDR) circuit. [11 Sep 2008]
A DSP Based 10BaseT/100BaseTX Ethernet Transceiver in a 1.8v, 0.18um CMOS Technology
White Paper This white paper describes a DSP based 10BaseT/100BaseTX ethernet physical layer interface in a 1.8v 0.18um single-poly 5-level metal CMOS technology. The DSP architecture allows for a robust perfomance for cable lengths... [25 Feb 2004]
Intel boosts Celeron chips with CMOS technology
News Based on its own 0.25 micron CMOS (Complementary Metal Oxide Semiconductor) process technology, the latest additions include a 32Kbyte (16Kbyte/16Kbyte) non-blocking, level-one cache, aimed at providing quicker access to... [05 Jan 1999]
Fully Integrated CMOS Radios From RF to Millimeter Wave Frequencies
White Paper This paper reviews recent CMOS demonstrations of capabilities for Radio Frequency (RF), microwave, and millimeter wave circuits from 1 GHz to 100 GHz, advances in on-die isolation structures for integrating radio's... [17 Jan 2005]
A Multiphase PLL for 10 Gb/s Links in SOI CMOS Technology
White Paper The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6 - 12.8 GHz at a supply voltage of 1.7 V. This paper presents a multiphase PLL designed for a 10x10 Gb/s serial link bundle that is... [11 Apr 2005]
Ultra-High-Speed CMOS Interface Technology
White Paper Fujitsu has already marketed high-speed network interface products such as the 10 G Ethernet and has recently developed a CMOS interface that accommodates high-speed data transfer at 6.4 Gb/s per signal line to increase... [02 Jun 2006]
Bypass the BIOS password by hacking your CMOS settings
White Paper Recover from a CMOS memory-affecting virus or work around a boot-time password by making BIOS forget all it once knew. This downloadable hack from PC Hacks: 100 Industrial-Strength Tips & Tools, by Jim Aspinwall, shows... [17 May 2006]
Design Rules for Quantum Imaging Devices: Experimental Progress Using CMOS Single Photon Detectors
White Paper This paper reports on experimental progress using SPAD (Single Photon Avalanche Diode) arrays of the design and fabricated in CMOS (Complementary Metal Oxide Semiconductor) technology. They have also been particularly... [07 Jan 2007]
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization
White Paper The complexity in timing optimization of high-performance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process... [10 Jul 2008]
Design and Analysis Methodology for a Bluetooth Sub-Micron CMOS PA
White Paper This paper presents the methodology to design a Power Amplifier in sub-micron CMOS technology, taking into account all the parasitic effects. The PA has been integrated in a double oxide 0.18 um RF CMOS. [09 Aug 2008]
Extended 90 nm CMOS Technology With High Manufacturability for High-Performance, Low-Power, RF/Analog Applications
White Paper High-density, 90 nm CMOS technology has been suggested for generic, low-voltage, high-performance applications. This paper, describes some strategies for extending the previous technology in order to fabricate the... [29 Feb 2008]
Gate Dielectric Scaling for High-Performance CMOS: From SiO2 to High-K
White Paper The silicon industry has been scaling SiO2 aggressively for the past 15 years for low power, high-performance CMOS logic applications. There are many challenges reported in literature in replacing SiO2 with high-K for... [07 Nov 2007]
Selecting the Right CMOS Analog Switch
White Paper First developed about 25 years ago, integrated analog switches often form the interface between analog signals and a digital controller. This tutorial presents the theoretical basis for analog switches and describes some common... [25 Feb 2004]
Integration of High-Performance Transistors, High-Density SRAMs, and 10-Level Copper Interconnects Into a 90 nm CMOS Technology
White Paper This paper presents a 40 nm-gate-length transistor, an ultra-high-density 6T SRAM cell, 10-level Cu interconnects, and Very-Low-K (VLK) dielectrics for high-performance microprocessor applications. The key process features are 193 nm... [01 Mar 2008]
Integrating CMOS Designs in GSM Front-Ends
As GSM phones represent over 60 percent of worldwide handset sales and are entirely based on switched front-ends, the paper will focus on GSM system requirements and discuss how different switching technologies address them. [10 Nov 2005]
