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Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors
White Paper Snooping protocols send requests to the maximal destination set (i.e.all processors), reducing latency for cache-to-cache misses at the expense of increased traffic. Directory protocols send requests to the minimal destination set, reducing... [11 Jul 2008]
Performance, Area and Bandwidth Implications on Large-Scale CMP Cache Design
White Paper The goal of this paper is to explore the cache design space for LCMP platforms. The performance and scalability of these architectures is highly dependent on the design of the cache hierarchy. CAAM first considers two important constraints and... [08 Jul 2008]
Cornell Theory Center: Demonstrating the Value of Intel Itanium Architecture in High Performance Computing
White Paper The Intel Itanium architecture is an outstanding choice for HPC solutions, offering a 64-bit address space, outstanding floating-point performance and memory bandwidth, and large cache memories. Equally important, the Itanium processor family... [03 Jul 2008]
APEX CAM as Cache for External CAM
White Paper In designs that use larger,discrete content-addressable memory (CAM)devices, you can use embedded CAM as a cache block for an external CAM device to store more frequently requested data. This white paper describes how embedded CAM can be used with... [03 Jul 2008]
Cisco Wide Area Application Services (WAAS) Egress Methods
White Paper Web Cache Communication Protocol Version 2 (WCCPv2) gives IT organizations mechanism to transparently intercept and redirect network traffic to a nearby network device, such as a Cisco Wide Area Application Engine (WAE) Appliances running Cisco... [13 Jun 2008]
DNS security still "as vulnerable as ever"
News Recursion can leave DNS systems vulnerable to DNS cache poisoning and amplification attacks that can "bring down major networks", said Infoblox. The survey was based on a sample that included five per cent of the IPv4 address space - nearly 80... [21 Nov 2007]
FreeLoader: Scavenging Desktop Storage Resources for Scientific Data
White Paper This paper presents the FreeLoader framework, which aggregates unused desktop storage space and I/O bandwidth into a shared cache/scratch space, for hosting large, immutable datasets and exploiting data access locality. [23 Aug 2007]
Context Switching and IPC Performance Comparison Between uClinux and Linux on the ARM9 Based Processor
White Paper Therefore Linux should flush entire cache and TLB on each context switch which is very costly.uClinux, however, contents of caches and a TLB are valid even after context-switch because the same address space is shared among all processes. [01 Apr 2007]
Decision Speed: Table Compression in Action
White Paper It will drastically reduce the disk space and buffer cache requirements, and in many cases improve query performance, especially on I/O bound systems. Table Compression, a feature introduced in Oracle9i Database Release 2, can compress entire... [11 Oct 2006]
Microsoft set for security shopping spree
News Whale's SSL encryption particularly interested the software giant, as it complements Microsoft's application-layer firewall, VPN and web cache software, ISA Server 2006, according to Kutwaroo. Buss said: "Microsoft is not proven in the enterprise... [03 Aug 2006]
Intel unveils 'lean, mean, AMD-busting' Xeon
News The features of Intel's new Core micro-architecture, such as a larger and more sophisticated cache memory design and a faster connection to memory, are responsible for the boost in performance over Intel's older dual-core server processors, Kilroy... [27 Jun 2006]
Intel refreshes mobile processor line up
News The chips also feature Hyper-Threading Technology support, a 1MB Level 2 cache and upgrades to Intel's NetBurst design architecture. The new Celeron M processor 340, which will be targeted at thin and light notebooks, operates at 1.5GHz and offers... [02 Jun 2004]
HP Doubles Up on Madison
White Paper bus converter and cache controller chip that makes the daughterboard play nice with the rest of the system. They are powered by a single voltage regulator module (VRM) to save space. This paper talks about the HP mx2 dual processor module (codenamed ? [30 May 2004]
Gravitational Data Falls From GRACE to be Processed by Growing TACC
White Paper TACC uses a 1.3-terabyte (TB) data cache on the front end, managed by SGI Data Migration Facility, to deliver online access speeds for current project data. The University of Texas at Austin (UT Austin) carries the torch for space-related... [24 Apr 2004]
Table Compression in Oracle9i Release 2: A Performance Analysis
White Paper It will drastically reduce the disk space and buffer cache requirements. Using these schemas the two main sections of this paper analyze how table compression can result in tremendous space saving and investigate the impact of table compression on... [02 Mar 2004]
