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Photos: Intel's latest technology on show
Photo Intel showed this first look at a transistor built with its 32-nanometre manufacturing process. Sean Maloney, newly-promoted and heir apparent to CEO Paul Otellini in the eyes of many, was the first to take the stage at... [28 Sep 2009]
Peter Cochrane's Blog: Software - keep it short and sweet
Comment We have been used to seeing transistor density and data storage double (thereabouts) year-on-year. Compiled in a car park in Redcar UK, edited in my garden on a warm summer evening, and dispatched to silicon.com from The... [07 Sep 2009]
The PSP Model in RF CMOS Design
White Paper While the Penn State Philips (PSP) transistor model is rightly hailed as an excellent alternative to traditional BSIM models for RFIC design, RF designers need to be aware of how PSP models relate to actual device behavior. [11 Jun 2009]
Design of GaN HEMT Transistor Based Amplifiers for 5-6 GHz WiMAX Applications
White Paper 2.5 and 5 Watt average power (15 and 30 Watt peak power) GaN HEMT amplifiers for WiMAX signal protocols have been designed and fabricated for use in the 5.5 to 5.8 GHz band. The 2.5 Watt PA produces 11 dB of gain and the 5 Watt PA... [22 Apr 2009]
Managing the Impact of Increasing Microprocessor Power Consumption
White Paper The power dissipation of modern processors has been rapidly increasing along with increasing transistor count and clock frequencies. This trend is the result of the significant increase in transistor... [03 Dec 2008]
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
White Paper It explores the behavior of the 3D-integrated arithmetic circuits with increasing issue-width (parallel execution capability), transistor sizing, and temperature. It demonstrates that the 3D-integrated circuits have less... [11 Jul 2008]
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization
White Paper In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is proposed. The complexity in timing optimization of... [10 Jul 2008]
Photos: Say hello to Intel's little helpers
Photo Its 32-nanometer chipsets, set for production in 2009, enable more chips per wafer, faster transistors, and less energy per transistor than their 45-nanometer predecessors, which have been shipped inside 15 million... [18 Jun 2008]
IBM POWER6 Microprocessor Physical Design and Design Methodology
White Paper The IBM POWER6e microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency,... [09 Apr 2008]
Carbon Nanotube Bumps for Thermal and Electric Conduction in Transistor
White Paper The continuous miniaturization of semiconductor chips has rapidly improved the performance of semiconductor products. However, thermal issues that affect semi- conductor chips are becoming more serious. [15 Feb 2008]
Photos of the month - January 2008
Photo This shows the three Bell Labs scientists who invented the transistor: John Bardeen, Walter Brattain and William Shockley. Picture credit: 192.com silicon.com looked back at the history of one of the cornerstones of... [30 Jan 2008]
Photos: Modern computing balancing on the head of a pin?
Photo They don't make them like this anymore - silicon.com casts an eye back over the ever-shrinking transistor, the invention that became the cornerstone of computing and the modern world. The transistor was... [29 Jan 2008]
Atomic storage to shrink your PC?
News Researchers at IBM will have two papers published in the journal Science this week detailing how it may be possible to use individual atoms, or groups of atoms, to store data or act as a transistor. The work revolves... [31 Aug 2007]
Peter Cochrane's Blog: Robots with guns
Comment But soon World War Two, the invention of the transistor, the space race and the arrival of the microprocessor quickly made it all very real. Written at a quiet café on the outskirts of Cambridge, UK and dispatched to... [07 Aug 2007]
Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low-Power Logic Applications
White Paper The major potential advantage of using a III-V quantum-well field-effect transistor as a logic transistor is that it can be operated under very low supply voltage(e.g. This paper highlights the... [19 Jul 2007]
