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By Michael Kanellos, 27 August 2003 08:56

NEWS IBM and the University of Texas plan to collaborate on building a processor capable of churning out more than one trillion calculations per second - faster than many of today's top supercomputers. The TRIPS (Tera-op Reliable Intelligently adaptive Processing System) architecture for the chip was conceived of by researchers at the university. But it will be brought to reality through a collaborative effort with IBM's Austin Research Lab, according to IBM. The Defense Advanced Research Projects Agency (DARPA) is funding the effort with an $11.1m grant. At the heart of the TRIPS architecture is a new concept called "block-oriented execution", IBM said. Whereas most chips can handle just a few calculations at a time, a processor based on TRIPS architecture will be able to perform large blocks of them simultaneously, the company said. A chip capable of performing 1 trillion operations - a tera-op - won't emerge from the project until 2010. However, researchers are readying a prototype chip with four processor cores - the computing unit inside a processor - that is expected in less than three years. These cores will be designed to churn 16 operations per clock cycle each, for a total of 64 operations per clock cycle. The prototype chip is expected to operate at 500MHz, which means its internal clock should complete 500 million cycles per second. That adds up to about 32 billion operations per second, theoretically. TRIPS chips prototypes will be running in the lab by December 2005, IBM added. By 2010, the research team expects to accelerate the chip's speed to 10GHz and be capable of performing one trillion operations, or calculations, per second. Michael Kanellos writes for News.com