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An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Category: Desktops, Laptops and OS, Servers and Server OS

Overview Embedded processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trading-off requirements. By using parallel and systolic algorithmic techniques, despite of its simple architecture IMAP achieves to exploit not only the straightforward per image row Data Level Parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, under the use of an explicit parallel C language (1DC).

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Publisher: Institute of Electrical and Electronics Engineers
File Format: PDF
Date Published: Oct 22, 2008
Format: White Papers
Topics: Parallel Processing, Processors

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