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A SystemC Transaction Level Model for the MIPS R3000 Processor

Category: Desktops, Laptops and OS, Servers and Server OS

Overview Processor cores in embedded applications build today the cornerstone of System-on-Chip designs. Among the most successful RISC (Reduced Instruction Set Computer) cores are the MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. This paper designs and verifies a Transaction Level Modeling (TLM) architecture of the MIPS R3000 in SystemC. The TLM in SystemC is adopted so that abstract data types can be used for higher level modeling and faster simulation. The processor is implemented such that the instruction and data caches contain all the necessary instructions and data to eliminate complex memory access management, respectively.

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Publisher: Concordia University
File Format: PDF
Date Published: Nov 26, 2008
Format: White Papers
Topics: RISC-Based Servers, Processors

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