White Papers
Design of a DSP Unit for 32-Bit Embedded EISC Microprocessor
Category: Desktops, Laptops and OS
Tags: microprocessor
Overview This paper designed a low hardware cost and fast DSP unit for 32-bit embedded EISC (Expanded Instruction Set Computer) microprocessor. The DSP unit operates as a functional unit of an integer core. This architecture can reduce the hardware cost and control easily the pipeline of the processor. The MAC/MAS unit was designed using hybrid radix-4/radix-8 Booth algorithm to reduce the hardware cost. All of the DSP instructions except DSP XY memory MAC/MAS instructions are executed in single cycle and have single cycle throughput. This DSP unit was modeled in Verilog HDL and synthesized with 0.35 ?m standard cell libraries after verifications. Occupied area is 21,850 equivalent gates. It operates at 63 MHz clock speed under the worst-case conditions.
- Publisher
- Yonsei University
- File Format
- Date Published
- Dec 4, 2008
- Format
- White Papers
- Topics
- Embedded Microprocessors, Microprocessors
Similiar White Papers
NAND Flash Applications Design Guide
This detailed white paper from Toshiba America Electronic Components, Inc. provides product designers, engineers, and de
Publisher: Toshiba | Tags: developers, management, nand
Comparing Multi-Core Processors for Server Virtualization
Rob Carpenter shares highlights from his whitepaper on his data center virtualization performance testing of the new Qua
Accelerating EDA Application Performance with 45nm Quad-Core Processors
Intel IT and Synopsys conducted a joint performance assessment of 64-bit Intel multi-core platforms running Synopsys Pro
Improving the Performance of Embedded Superscalar Microprocessors by Adding Partial Pipelines
This paper introduces adding a "Partial" pipeline to a base embedded superscalar microprocessor implementation to achiev
Publisher: University of York | Tags: benchmark, ip, microprocessor
Energy Based Analysis of Embedded Microprocessor Cache Design
This paper focuses on performing a broad exploration of the embedded processor cache design space in order to determine
Publisher: University of California
Yonsei University White Papers
A Giga-b/s CMOS Clock and Data Recovery Circuit With a Novel Adaptive Phase Detector
In this paper, a new clock and Data Recovery Circuit (CDR) is proposed for the application of data communication systems
Publisher: Yonsei University | Tags: data, verified
Performance Analysis According to the Change of Cluster Size in Large Scale Wireless Sensor Networks
In large scale sensor networks, scalability and robustness are very important, and sensor nodes are also highly power co
Publisher: Yonsei University | Tags: data, qos
Evolutionary Design of Intrusion Detection Programs
Intrusion detection is the process of monitoring the events occurring in a computer system or network and analyzing them
Publisher: Yonsei University | Tags: network
Featured white papers
-
The Value of Location Intelligence in the Communications Industry
Public Services are under pressure, the challenge is to do more with less. How do you improve citizen satisfaction, increase cost efficiencies and improve service delivery? The power of location intelligence is helping many local authorities...
-
Best Practices for Translating Customer Satisfaction into Revenue
Today's support organisations are focused on two top-level metrics: financial results and customer satisfaction. For most, it's easy to track financial performance, but customer satisfaction is akin to speaking a foreign language...
-
HP print solutions and 3M
The objective for 3M was to optimize office printing infrastructure at 3M locations worldwide, reduce total cost and environmental footprint. Some of the business benefits acheived by switching to HP print solutions...
-
Check out these top business apps for your iPhone
-
Inside a Microsoft datacentre
-
Green IT without losing your edge
-
Peter Cochrane's latest video blog
-
What you need to know about Windows 7