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Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams

Overview This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Raw supports both ILP and streams by routing operands between architecturally-exposed functional units over a point-to-point scalar operand network. This network offers low latency for scalar data transport.

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Publisher
Massachusetts Institute of Technology
File Format
PDF
Date Published
Dec 4, 2008
Format
White Papers
Topics
Application Development, Microprocessors

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