White Papers
Optimizing Pipeline for a RISC Processor With Multimedia Extension ISA
Overview The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a Data Flow Graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI.
- Publisher
- Zhejiang University
- File Format
- Date Published
- Dec 4, 2008
- Format
- White Papers
- Topics
- RISC-Based Servers, Processors, Multimedia
Zhejiang University White Papers
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