White Papers

A Full On-Chip CMOS Clock Data Recovery IC for OC-192 Applications

Tags: data

Overview In this paper, a fully integrated OC-192 Clock-Data Recovery (CDR) architecture in standard 0.18?m CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The measured RMS jitter of the recovered data is 0.74ps with a Bit-Error Rate (BER) less than 10-12 when the input PRBS data pattern has a pattern length of 215-1 and a total horizontal eye closure of 0.54 UIpp due to the added ISI distortion by passing data through 9 inches FR4 PCB trace.

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Publisher: Institute of Electrical and Electronics Engineers
File Format: PDF
Date Published: Oct 22, 2008
Format: White Papers
Topics: Data Recovery - Security, Knowledge and Data Management

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