White Papers

Open-Loop Clock and Data Recovery Systems

Overview CDR circuits typically use PLLs, but their complexity presents several design challenges : the input data stream is random and is usually in Non-Return-to-Zero (NRZ) data format, and little energy exists at the clock frequency that is to be recovered. Consequently, the choice of phase detector is very limited. Binary phase detectors are simpler in design but generate significant discontinuity on the control voltage of the VCO at each data transition edge. Linear phase detectors do not affect the VCO when they are phase-locked, but typically produce detection dead zone, which is due to short "UP" pulses, at high frequency applications; The charge-pump current mismatch produces unequal "UP" and "DOWN" signal strengths, which causes the phase to drift from desired values.

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Publisher: Cornell University
File Format: PDF
Date Published: Oct 22, 2008
Format: White Papers
Topics: Data Recovery - Security, Knowledge and Data Management

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