White Papers

Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems

Overview Clock recovery using Phase-Locked Loops (PLL) with binary (bang-bang) or ternary-quantized phase detectors has become increasingly common starting with the advent of fully monolithic Clock and Data Recovery (CDR) Circuits off late. Bang-bang CDR circuits have the unique advantages of inherent sampling phase alignment, adaptability to multi-phase sampling structures, and operation at the highest speed at which a process can make a working flip-flop. This paper gives insight into the behavior of the nonlinear bang-bang PLL loop dynamics, giving approximate equations for loop jitter, recovered clock spectrum, and jitter tracking performance as a function of various design parameters.

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Publisher: Agilent
File Format: PDF
Date Published: Oct 7, 2008
Format: White Papers
Topics: Data Recovery - Security

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