White Papers

Simulation Model of Digital Clock and Data Recovery for Strongly Disturbed Signals

Overview The paper describes VHDL-AMS simulation model of a digital link (with a signal source) together with "Software" clock and data recovery module and common recovery circuit incorporating a PLL. Performance of both methods is compared and discussed. Models were created to help to improve the software recovery method. All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

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Publisher: Brno University of Technology
File Format: PDF
Date Published: Oct 22, 2008
Format: White Papers
Topics: Data Recovery - Security

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