White Papers
High-Bandwidth Address Translation for Multiple-Issue Processors
Category: Desktops, Laptops and OS, Networking and Communications
Tags: microprocessor
Overview In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth demands on the address translation mechanism. Most current microprocessor designs meet this demand with a multi-ported TLB. While this design provides an excellent hit rate at each port, its access latency and area grow very quickly as the number of ports is increased. As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency. This paper presents four high-bandwidth address translation mechanisms with latency and area characteristics that scale better than a multi-ported TLB design.
- Publisher
- University of Wisconsin-Madison
- File Format
- Date Published
- Jul 11, 2008
- Format
- White Papers
- Topics
- Microprocessors, Processors, Bandwidth Issues
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