White Papers

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

Overview This paper presents a general architecture for digital Clock and Data Recovery (CDR) for high speed binary links. The architecture is based on replacing the analog loop filter and VCO in a typical analog PLL-based CDR with digital components. They provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Finally, measured results are presented that corroborate the modeled results.

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Publisher
Synopsys
File Format
PDF
Date Published
Oct 1, 2008
Format
White Papers
Topics
Data Recovery - Security, Software Engineering

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